0683dde5d3
cargo-xwin drives the Windows MSVC cross-compile via clang-cl, under which CMake sets MSVC=1 — causing libopus 1.3.1's `if(NOT MSVC)` guards to skip the per-file `-msse4.1` / `-mssse3` COMPILE_FLAGS that its x86 SIMD source files need. Clang-cl (unlike real cl.exe) still honors Clang's target-feature system, so those files then fail to compile with "always_inline function '_mm_cvtepi16_epi32' requires target feature 'sse4.1'" errors across silk/NSQ_sse4_1.c, NSQ_del_dec_sse4_1.c, and VQ_WMat_EC_sse4_1.c. Earlier attempts to fix this downstream (cargo-xwin toolchain file, override.cmake CMAKE_C_COMPILE_OBJECT <FLAGS> replace, CFLAGS env vars) all failed because cargo-xwin rewrites override.cmake from scratch on every `cargo xwin build` invocation and cmake-rs's -DCMAKE_C_FLAGS= assembly happens before toolchain FORCE sets propagate. Fixing it upstream at the source: vendor audiopus_sys 0.2.2 into vendor/audiopus_sys, patch its bundled opus/CMakeLists.txt to introduce an MSVC_CL var (true only when CMAKE_C_COMPILER_ID == "MSVC", i.e. real cl.exe), and flip the eight `if(NOT MSVC)` SIMD guards to `if(NOT MSVC_CL)`. Clang-cl then gets the GCC-style per-file flags and the SSE4.1 sources build cleanly. Also flip the `if(MSVC)` global /arch block at line 445 to `if(MSVC_CL)` so only cl.exe applies /arch:AVX and clang-cl relies purely on per-file flags (no global/per-file mixing). Wire via [patch.crates-io] in the workspace root Cargo.toml; the patch is resolved relative to the workspace root as `vendor/audiopus_sys`. Upstream context: xiph/opus#256, xiph/opus PR #257 (both stale). Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
221 lines
6.1 KiB
C
221 lines
6.1 KiB
C
/***********************************************************************
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Copyright (c) 2006-2011, Skype Limited. All rights reserved.
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Copyright (c) 2013 Parrot
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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- Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of Internet Society, IETF or IETF Trust, nor the
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names of specific contributors, may be used to endorse or promote
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products derived from this software without specific prior written
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permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***********************************************************************/
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#ifndef SILK_MACROS_ARMv5E_H
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#define SILK_MACROS_ARMv5E_H
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/* This macro only avoids the undefined behaviour from a left shift of
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a negative value. It should only be used in macros that can't include
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SigProc_FIX.h. In other cases, use silk_LSHIFT32(). */
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#define SAFE_SHL(a,b) ((opus_int32)((opus_uint32)(a) << (b)))
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/* (a32 * (opus_int32)((opus_int16)(b32))) >> 16 output have to be 32bit int */
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#undef silk_SMULWB
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static OPUS_INLINE opus_int32 silk_SMULWB_armv5e(opus_int32 a, opus_int16 b)
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{
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int res;
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__asm__(
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"#silk_SMULWB\n\t"
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"smulwb %0, %1, %2\n\t"
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: "=r"(res)
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: "r"(a), "r"(b)
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);
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return res;
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}
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#define silk_SMULWB(a, b) (silk_SMULWB_armv5e(a, b))
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/* a32 + (b32 * (opus_int32)((opus_int16)(c32))) >> 16 output have to be 32bit int */
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#undef silk_SMLAWB
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static OPUS_INLINE opus_int32 silk_SMLAWB_armv5e(opus_int32 a, opus_int32 b,
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opus_int16 c)
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{
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int res;
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__asm__(
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"#silk_SMLAWB\n\t"
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"smlawb %0, %1, %2, %3\n\t"
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: "=r"(res)
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: "r"(b), "r"(c), "r"(a)
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);
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return res;
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}
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#define silk_SMLAWB(a, b, c) (silk_SMLAWB_armv5e(a, b, c))
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/* (a32 * (b32 >> 16)) >> 16 */
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#undef silk_SMULWT
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static OPUS_INLINE opus_int32 silk_SMULWT_armv5e(opus_int32 a, opus_int32 b)
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{
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int res;
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__asm__(
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"#silk_SMULWT\n\t"
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"smulwt %0, %1, %2\n\t"
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: "=r"(res)
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: "r"(a), "r"(b)
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);
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return res;
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}
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#define silk_SMULWT(a, b) (silk_SMULWT_armv5e(a, b))
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/* a32 + (b32 * (c32 >> 16)) >> 16 */
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#undef silk_SMLAWT
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static OPUS_INLINE opus_int32 silk_SMLAWT_armv5e(opus_int32 a, opus_int32 b,
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opus_int32 c)
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{
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int res;
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__asm__(
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"#silk_SMLAWT\n\t"
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"smlawt %0, %1, %2, %3\n\t"
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: "=r"(res)
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: "r"(b), "r"(c), "r"(a)
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);
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return res;
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}
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#define silk_SMLAWT(a, b, c) (silk_SMLAWT_armv5e(a, b, c))
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/* (opus_int32)((opus_int16)(a3))) * (opus_int32)((opus_int16)(b32)) output have to be 32bit int */
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#undef silk_SMULBB
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static OPUS_INLINE opus_int32 silk_SMULBB_armv5e(opus_int32 a, opus_int32 b)
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{
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int res;
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__asm__(
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"#silk_SMULBB\n\t"
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"smulbb %0, %1, %2\n\t"
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: "=r"(res)
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: "%r"(a), "r"(b)
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);
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return res;
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}
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#define silk_SMULBB(a, b) (silk_SMULBB_armv5e(a, b))
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/* a32 + (opus_int32)((opus_int16)(b32)) * (opus_int32)((opus_int16)(c32)) output have to be 32bit int */
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#undef silk_SMLABB
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static OPUS_INLINE opus_int32 silk_SMLABB_armv5e(opus_int32 a, opus_int32 b,
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opus_int32 c)
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{
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int res;
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__asm__(
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"#silk_SMLABB\n\t"
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"smlabb %0, %1, %2, %3\n\t"
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: "=r"(res)
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: "%r"(b), "r"(c), "r"(a)
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);
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return res;
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}
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#define silk_SMLABB(a, b, c) (silk_SMLABB_armv5e(a, b, c))
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/* (opus_int32)((opus_int16)(a32)) * (b32 >> 16) */
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#undef silk_SMULBT
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static OPUS_INLINE opus_int32 silk_SMULBT_armv5e(opus_int32 a, opus_int32 b)
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{
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int res;
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__asm__(
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"#silk_SMULBT\n\t"
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"smulbt %0, %1, %2\n\t"
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: "=r"(res)
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: "r"(a), "r"(b)
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);
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return res;
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}
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#define silk_SMULBT(a, b) (silk_SMULBT_armv5e(a, b))
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/* a32 + (opus_int32)((opus_int16)(b32)) * (c32 >> 16) */
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#undef silk_SMLABT
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static OPUS_INLINE opus_int32 silk_SMLABT_armv5e(opus_int32 a, opus_int32 b,
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opus_int32 c)
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{
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int res;
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__asm__(
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"#silk_SMLABT\n\t"
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"smlabt %0, %1, %2, %3\n\t"
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: "=r"(res)
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: "r"(b), "r"(c), "r"(a)
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);
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return res;
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}
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#define silk_SMLABT(a, b, c) (silk_SMLABT_armv5e(a, b, c))
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/* add/subtract with output saturated */
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#undef silk_ADD_SAT32
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static OPUS_INLINE opus_int32 silk_ADD_SAT32_armv5e(opus_int32 a, opus_int32 b)
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{
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int res;
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__asm__(
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"#silk_ADD_SAT32\n\t"
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"qadd %0, %1, %2\n\t"
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: "=r"(res)
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: "%r"(a), "r"(b)
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);
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return res;
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}
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#define silk_ADD_SAT32(a, b) (silk_ADD_SAT32_armv5e(a, b))
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#undef silk_SUB_SAT32
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static OPUS_INLINE opus_int32 silk_SUB_SAT32_armv5e(opus_int32 a, opus_int32 b)
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{
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int res;
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__asm__(
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"#silk_SUB_SAT32\n\t"
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"qsub %0, %1, %2\n\t"
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: "=r"(res)
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: "r"(a), "r"(b)
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);
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return res;
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}
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#define silk_SUB_SAT32(a, b) (silk_SUB_SAT32_armv5e(a, b))
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#undef silk_CLZ16
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static OPUS_INLINE opus_int32 silk_CLZ16_armv5(opus_int16 in16)
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{
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int res;
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__asm__(
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"#silk_CLZ16\n\t"
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"clz %0, %1;\n"
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: "=r"(res)
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: "r"(SAFE_SHL(in16,16)|0x8000)
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);
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return res;
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}
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#define silk_CLZ16(in16) (silk_CLZ16_armv5(in16))
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#undef silk_CLZ32
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static OPUS_INLINE opus_int32 silk_CLZ32_armv5(opus_int32 in32)
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{
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int res;
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__asm__(
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"#silk_CLZ32\n\t"
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"clz %0, %1\n\t"
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: "=r"(res)
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: "r"(in32)
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);
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return res;
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}
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#define silk_CLZ32(in32) (silk_CLZ32_armv5(in32))
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#undef SAFE_SHL
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#endif /* SILK_MACROS_ARMv5E_H */
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